FPGA

以下ソース

filter_top.v

`timescale 1ns / 1ps
module filter_top(
	input wire clk,
	input wire [7:0] ssw,
	output wire [3:0] led
    );
wire [3:0] a,b;
wire [3:0] cout;

//4bit fullAdder
//FullAdder回路接続
assign a = ssw[7:4];
assign b = ssw[3:0];


FullAdder f0(.CIN(0),.A(a[0]),.B(b[0]),.Q(led[0]),.COUT(cout[0]));
FullAdder f1(.CIN(cout[0]),.A(a[1]),.B(b[1]),.Q(led[1]),.COUT(cout[1]));
FullAdder f2(.CIN(cout[1]),.A(a[2]),.B(b[2]),.Q(led[2]),.COUT(cout[2]));
FullAdder f3(.CIN(cout[2]),.A(a[3]),.B(b[3]),.Q(led[3]),.COUT(cout[3]));


endmodule
	      

FullAdder.v

`timescale 1ns / 1ps
module FullAdder(
	input wire CIN,
	input wire A,
	input wire B,
	output wire Q,
	output wire COUT
    );
	assign Q = A ^ B ^ CIN;
	assign COUT = (A & B) | (B & CIN) | (CIN & A);


endmodule
      
      

filter_top.ucf

NET "clk" LOC = L15;
NET "led(0)" LOC = U18;
NET "led(1)" LOC = M14;
NET "led(2)" LOC = N14;
NET "led(3)" LOC = L14;

NET "ssw(7)" LOC = E4;
NET "ssw(6)" LOC = T5;
NET "ssw(5)" LOC = R5;
NET "ssw(4)" LOC = P12;
NET "ssw(3)" LOC = P15;
NET "ssw(2)" LOC = C14;
NET "ssw(1)" LOC = D14;
NET "ssw(0)" LOC = A10;